The present invention relates to an evaluation single-chip microcomputer used for debugging application programs for a single-chip microcomputer in the process of development of the application programs. A single-chip microcomputer is a microcomputer with a CPU (central processing unit), a storage device, and input/output devices which are all built into a single chip of an integrated circuit.
An example of an evaluation single-chip microcomputer in the prior art is shown in FIG. 1. The illustrated microcomputer 1 comprises an internal bus 2, eight external bus terminals 2a connected to the internal bus 2 for input of instructions, twelve or more address output terminals 3 connected by leads to the inside of the circuit, output terminals 4-1 to 4-5 connected by leads to the internal circuit, a CPU (central processing unit) including an operation section and control section, and a storage unit.
The operation section of the CPU comprises temporary registers (TR1, TR2) 5, 6 for temporarily storing data in accordance with write signals WTR1, WTR2, an ALU (arithmetic logic unit) 7 performing arithmetic operations and logic operations on the outputs of the registers 5, 6. a carry flag register 8 indicating the carry status of the ALU 7, and an accumulator 9 for temporarily storing the result of the operations in accordance with a write signal WACC and providing its contents to the internal bus 2, the temporary register 6 and the output terminals 4-3. The control section of the CPU comprises an instruction register 10 for temporarily storing an instruction supplied through the bus 2 in accordance with a write signal WIR, and a control circuit 11 for decoding the output of the instruction register 10 to produce various control signals including various write signals WTR1, WTR2, WACC, WIR, WM and WD, and increment and decrement signals PC+1, D+1 and D-1. The output of the instruction register 10 is also supplied to the external terminals 4-4.
The storage unit comprises a data memory 12 in the form of a read/write memory (RAM) which stores data in accordance with the write signal WM and produces its contents onto the bus 2 and the output terminal 4-2, and a program memory 13 in the form of a read-only memory (ROM) which stores programs and produces its contents onto the bus 2 and the output terminals 4-5. The addresses of the memories 12 and 13 are given from a data pointer 14 and a program counter (PC) 15, respectively. That is, the data pointer 14 is a register which stores an address of the data memory 12 in which the data should be written next or from which the data should be read next. The data pointer 14 stores the data (address) from the bus 2 in accordance with the write signal WD. The data pointer 14 also increments or decrements its content in accordance with the increment signal D+1 or decrement signal D-1. The output of the data pointer 14 is supplied to the data memory 12 and the output terminal 4-1. The program counter 15 is a register which stores an address of the program memory 13 from which an instruction should be read. The program counter 15 increments its content by 1 each time an increment signal PC+1 is applied from the control circuit 11. The output of the program counter 15 is supplied to the program memory 13 and the address output terminal 3. An essential distinction of the above described evaluation microcomputer from an ordinary microcomputer is the provision of output terminals 4-1 to 4-5 through which various signals can be output to external circuitry used for the evaluation tests.
When debugging of the application program to be evaluated is carried out using the evaluation microcomputer described above, an external memory 20 in the form of a ROM storing the application program is connected to the external bus terminals 2a and the address output terminals 3. The program is performed and whether the microcomputer operates as desired is tested by examining the various data as output through the output terminals.
For instance, when an instruction of the application program for transferring the content of the accumulator 9 to the data pointer 14 is to be executed, the instruction is read from the external memory 20 onto the internal bus 2, and the instruction on the internal bus 2 is written in the instruction register 10 in accordance with the write signal WIR. Since the content of the instruction register 10 is output through the output terminals 4-4, it can be examined outside of the microcomputer I. Next, the content of the instruction register 10 is decoded at the control circuit 11, from which the increment signal PC+1 is supplied to the program counter 15. The program counter 15 then supplies the next address to the external memory 20 and causes the content to be output onto the internal bus 2. The instruction on the internal bus 2 is again stored in the instruction register 10 and decoded at the control circuit 11. In accordance with the signal WACC then produced from the control circuit 11, the content of the accumulator 9 is output to the internal bus 2 and the output terminals 4-3. In accordance with the write signal WD also produced from the control circuit 11, the data on the internal bus 2 is written in the data pointer 14 and the content of the data pointer 14 is output through the output terminals 4-1 to the outside. The content of the data pointer 14 can therefore be examined outside.
The above described microcomputer has the following drawbacks. First a large number of terminals are required, including normally twelve or more address output terminals 3, and normally eight external bus terminals 2a for accessing the external memory 20, and output terminals 4-1 to 4-5 for outputting the contents of the ALU 7, accumulator 9, the instruction register 10, and the memories 12, 13 whose contents need to be examined in real time outside of the microcomputer. The number of the terminals of the evaluation microcomputer is thus much greater than that of the ordinary (mass-produced) microcomputer. For instance, if the registers are of eight bits, 53 or more additional output terminals are required. The package required for encapsulating the evaluation microcomputer needs to be a pin grid array (PGA) array package or other expensive package. Moreover, the area required for the mounting and the number of wirings are large.
In addition, the design pattern of the evaluation microcomputer is much more complicated than the design patterns of the ordinary microcomputer. This is because of the larger number of the terminals and leads connected to them. It is therefore impossible to share the same pattern layout between the evaluation microcomputer and the ordinary microcomputer. That is, it is necessary to make a separate pattern layout design for the evaluation microcomputer. Such a design of course requires much labor and time. Moreover, manufacture of the evaluation microcomputer with the different pattern layout design requires additional labor and time.